1. Field of the Invention
The present invention relates to a microcomputer, particularly to a circuit for reading data from a memory thereof, and specifically to a technology to expand the operation range with respect to the power voltage and to make it possible to prevent the microcomputer from running out of control due to mis-recognition of the data which is read from a memory, by responding to the fluctuation in the system clock frequency, at that time of reading of the data from the internal memory of the microcomputer.
2. Description of the Related Art
A microcomputer of the prior art uses a clock called a system clock in order to smoothly carry out data exchange with built-in ROM and RAM and peripheral circuits, and further with a memory or other devices connected on the outside. Thus all circuits including the circuits provided in the microcomputer make reference to the system clock during input and output of data.
A general configuration of such a conventional microcomputer will be described below with reference to a block diagram of FIG. 1.
In FIG. 1, numeral 8 denotes the main body of a microcomputer.
The microcomputer 8 has a CPU 1, a ROM 2, a RAM 3 and peripheral circuits 4 built therein, which are interconnected by means of an address bus 5 for exchanging address signal ADD and a data bus 6 for exchanging data signal DATA.
Numeral 7 denotes a signal-line (called E signal line hereafter) for the system clock (called E signal hereafter) which is generated by a clock generating circuit 1C located in the CPU 1 and is transmitted to the ROM 2, the RAM 3 and the peripheral circuit 4.
FIG. 2 is a block diagram illustrative of an example of the internal constitution of the ROM 2.
In FIG. 2, numerals 5, 6 and 7 denote the address bus, the data bus and the E signal line described above, respectively.
Numeral 9 denotes an address decoding circuit, numeral 10 denotes a selector circuit, numeral 11 denotes a ROM transistor group, numeral 12 denotes a sense amplifier control circuit, numeral 13 denotes a sense amplifier circuit, numeral 14 denotes a word line which is an output signal line connecting from the address decoding circuit 9 to the ROM transistor group 11, numeral 15 denotes a memory transistor and numeral 16 denotes a bit line which is an output signal line connecting from the ROM transistor group 11 to the selector circuit 10.
The ROM transistor group 11 comprises a plurality of memory transistors 15 arranged in a matrix, each memory transistor 15 being connected to one word line 14 and one bit line 16. This means that one memory transistor 15 is identified by selecting one word line 14 and one bit line 16.
The address decoding circuit 9 selects one word line 14 by decoding an address signal ADD which is supplied from the address bus 5.
At the same time, the result of decoding the address signal ADD by the address decoding circuit 9 is supplied also to the selector circuit 10 which thereby selects one or a plurality of bit lines 16.
The state, namely the content of the memory, of one or a plurality of transistors 15 thus specified by the selection of one word line 14 and one or a plurality of bit lines 16 is identified by the sense amplifier circuit 13, whereby data "1" or "0" is outputted to the data bus 6 depending on the result of identification.
Generally in the manufacturing process of the ROM 2, two types of transistors having different characteristics are made by either carrying out ion implantation or not for one memory transistor 15, while data "1" and "0" are assigned to the respective types, thereby to make a ROM which is a read-only memory with data being stored therein in advance.
Operation of the ROM 2 provided in the microcomputer 8 in case of outputting data with reference to the E signal including the progress with time will now be described below with reference to a timing chart shown in FIG. 3.
The operation of output ting data of the ROM 2 provided in the microcomputer 8 will be referred to simply as "readout of ROM data" in the description that follows.
In FIG. 3, symbol E denotes the E signal, ADD denotes the address signal given to the ROM 2, and DATA denotes the data signal which is read from the ROM 2.
When the E signal level becomes Vcc level which is the power voltage (called "H" level hereafter), the CPU 1 outputs the address signal ADD specifying the memory transistor 15 where the data to be read from the ROM 2 is stored, from the CPU I to the address bus 5. At this time, while the address signal ADD has an indefinite period (a period when the signal value is not established) t1 temporarily, the address decoding circuit 9 in the ROM 2 selects a word line 14 from among the ROM transistor group 11 in a period t2 that follows, thereby to select a group of memory transistors 15 which are connected to the selected word line 14.
At the same time, the selector circuit 10 specifies one bit line 16 thereby to select a set of memory transistors 15 which corresponds to the number of data bits required by the CPU 1 at a time, for example, from among the group of memory transistors which has been selected by means of the word line 14, as described above.
All these operations are carried out in a period when the E signal is at "H" level.
The series of the above operations is called the preparatory operation for data read-out.
Then after the E signal has returned to the GND level (called "L" level hereafter), the sense amplifier circuit 13 of the ROM 2 starts operation to identify, within a period t3, the state, "1" or "0", of each of the set of memory transistors 15 which have been selected, and accordingly outputs data signal "1" or "0" as the DATA to the data bus 6.
It is obvious from the above description, that read-out of data becomes impossible when the period of "L" level of the E signal is shorter than the period t3.
The series of operations described above is called the data read-out operation.
Although the above description assumes that the preparatory operation for data read-out and the data read-out operation are carried out according to the state of the E signal, "H" level or "L" level, for the sake of simplicity, read-out operation carried out immediately upon completion of the preparatory operation for data read-out is regarded as an equivalent operation, provided that a series of operations is completed within one cycle period of the E signal.
Now the operation of the sense amplifier circuit 13 shown in FIG. 2 will be described.
The sense amplifier circuit 13 identifies, via the bit line 16, the state of each memory transistor 15 which constitutes the ROM transistor group 11 of the ROM 2. A circuit diagram of FIG. 4 shows the specific constitution of the sense amplifier circuit 13.
In FIG. 4, symbols P1, P2 denote P channel transistors (called Pch-Tr hereafter) and N1, N2 denote N channel transistors (called Nch-Tr hereafter).
A source terminal of the Pch-Tr P1 is connected to Vcc which is the power voltage, a gate terminal thereof is connected to GND which is the ground potential and a drain terminal thereof is connected to a drain terminal of the Nch-Tr N1 and to a gate terminal of the Nch-Tr N2.
A source terminal of the Nch-Tr N1 is connected to GND, and a gate terminal thereof is connected to a source terminal of the Nch-Tr N2 and to the bit line 16 via the selector circuit 10.
A drain terminal of the Nch-Tr N2 is connected to a drain terminal of the Pch-Tr P2 and to an input terminal of an inverter INV1.
A source terminal of the Pch-Tr P2 is connected to Vcc and to GND, and a gate terminal thereof is connected to GND.
In the sense amplifier circuit 13 shown in FIG. 4, information of the bit line 16 corresponding to the state of the memory transistor, namely voltage VB, is inputted to the gate terminal of the Nch-Tr N1 and to the source terminal of the Nch-Tr N2. The input voltage VB causes the conductance of the Nch-Tr N1 to change, and accordingly the bias voltage VX which is applied to the Nch-Tr N2 is also changed.
The bias voltage VX can be determined as the intersection of a load curve IN1 of the Nch-Tr N1 with respect to the bias voltage VX and a load curve IP2 of the Pch-Tr P1 shown in a graph of FIG. 5.
Now the graph of FIG. 5 will be described below.
VTHP and VTHN are threshold voltages of the Pch-Tr and the Nch-Tr, respectively. .beta.P1 and .beta.N1 are coefficients representing the current driving capabilities of the Pch-Tr and the Nch-Tr, respectively.
(1) Characteristic of Pch-Tr P1
When inequality Vcc-VX&lt;Vcc-.vertline.VTHP.vertline. holds, then VTHP&lt;0 and hence EQU IP1=.beta.P1[(Vcc+VTHP)*(Vcc-VX)-(Vcc-VX).sup.2 /2].
When inequality Vcc-VX.gtoreq.Vcc-.vertline.VTHP.vertline. holds, then VTHP&lt;0 and hence EQU IP1=.beta.P1(Vcc+VTHP).sup.2 /2.
(2) Characteristic of Nch-Tr N1
When inequality VX&lt;VB-VTHN holds, then EQU IN1=.beta.N1[(VB-VTHN)*VX-VX.sup.2 /2 ]
When inequality VX.gtoreq.VB-VTHN holds, then EQU IN1=.beta.N1(VB-VTHN).sup.2 /2.
Values of .beta.P1 and .beta.N1 are uniquely determined by the channel length and the channel width of the transistor, and can be obtained from the following equation: EQU .beta.P1, .beta.N1=(.mu.e/.epsilon.ox/tox)*(Wc/ls)
where .mu.e: mobility
.epsilon.ox: dielectric constant of oxide film PA1 tox: thickness of oxide film PA1 Wc: channel width PA1 ls: channel length
FIG. 5 also shows a load curve of the Nch-Tr N1 when the voltage VB is at its maximum level and a load curve of the Nch-Tr N1 when the voltage VB is at its minimum level, as IN1B and IN1S, respectively.
It is obvious from the above description, that the bias voltage VX changes with the bit line voltage VB. That is, the bias voltage VX takes its minimum value VXL when the voltage VB reaches the maximum level, and takes its maximum value VXH when the voltage VB reaches the minimum level.
On the hand, voltage V0 at the input terminal of the inverter INV1 can be approximately determined as follows from the conductance GmN2 of the Nch-Tr N2 and the conductance GmP2 of the Pch-Tr P2. EQU V0=GmN2/(GmP2+GmN2)*(Vcc-VB)
Taking the fact that GmN2 is controlled by the bias voltage VX and that GmP2 is constant because the gate voltage is constant (GND) into consideration, it can be seen that the voltage V0 changes in accordance to the change in GmN2, namely to the change in the bias voltage VX. This means that conductance GmN2 of the Nch-Tr N2 has the minimum value and the voltage V0 has the maximum value when the bias voltage VX takes its minimum value VXL. And conductance GmN2 of the Nch-Tr N2 has the maximum value and the voltage V0 has the minimum value when the bias voltage VX takes its maximum value VXH. Consequently, when the threshold of the inverter INV1 is set at an intermediate level between the maximum and the minimum values of the voltage V0, it is made possible to read data "1" or "0" by means of the sense amplifier circuit 13 shown in FIG. 4.
Now the operation rate of the sense amplifier 13 will be briefly described below.
While change in the voltage at each point with time is neglected in the above description of operation of the sense amplifier circuit 13 shown in FIG. 4 for the sake of simplicity of description, every junction has parasitic load capacitance which results in a definite period of time taken before the voltage reaches the calculated level. The voltage which takes the longest time to reach the specified level because the point has the highest load capacity among these voltages is the gate voltage of the Nch-Tr N1, namely the voltage VB, which involves the load capacity of the bit line 16 added thereto.
It will be easily expected from the above description of the operation of the sense amplifier 13, that, a longer time taken before the voltage VB reaches the specified level results in a lower rate of the data read-out operation. Therefore, read-out rate varies depending on the capacity of the bit line 16, provided the sense amplifier circuit 13 having the same circuit constitution and the same circuit constant is used. This means that higher load capacity of the bit line 16 results in lower reading rate.
Recently there are microcomputers wherein a plurality of clocks having different frequencies can be used as the system clock. Also there are microcomputers wherein a plurality of voltages can be used as the power voltage. Further, in a microcomputer using a battery as the power source, there is a possibility of the power voltage to fluctuate.
However, in the conventional microcomputer as described above, normal read-out and transmission of the ROM data become impossible when the clock frequency increases to such an extent that the period during which the system clock (E signal) is at "L" level is shorter than the data read-out period t3. It has not been possible to know such a limitation of the read-out of ROM data beforehand in the prior art.
Also it has not been possible to know that the read-out operation margin is near its limitation due to a power voltage drop resulting in a lower rate of read-out from the ROM or a lower rate of data transmission to the data bus, or due to an increased clock frequency, namely that it has become impossible to read data within a specified clock cycle.
This means that a microcomputer using a battery as the power source fails to operate or malfunctions when the power voltage drops below to a certain level as the battery runs out.
Moreover, the range between the minimum level VXL and the maximum level VXH of the bias voltage VX becomes very narrow when the power voltage is low. In such a case, it is possible to increase the range between the minimum level VXL and the maximum level VXH of the bias voltage VX by increasing the values of .beta. of the Pch-Tr P1 and .beta. of the Nch-Tr N1. However, when the circuit constant, of the sense amplifier circuit is set so that the range becomes optimum when the power voltage Vcc is low, 3 V, for example, the power voltage Vcc being at the normal level, 5 V, for example, causes the currents IP1 and IN1 to increase and accordingly the power current to increase too, thereby making it difficult to obtain stable operation of the sense amplifier circuit when the process parameters, for example, VTHP and VTHN fluctuate.
Meanwhile, microcomputer makers produce microcomputers which operate on various power voltages according to the users' purposes, or manufacture microcomputers having system clocks of different frequencies. When it is desired to maintain an operation margin for various microcomputers having a wide range of operating power voltages or system clocks of various frequencies, it has been very difficult to set an optimum circuit constant which is appropriate for a wide range of power voltages by using one kind of sense amplifier circuit. Therefore, when designing microcomputers, it is necessary to design sense amplifier circuits having different characteristics corresponding to different, power voltages or to system clocks of different frequencies.